The networking of control units, sensor apparatus, and actuators with the aid of a network or communication system made up of a communication connection, in particular a bus, and corresponding communication modules, has drastically increased in recent years in the design of modern motor vehicles or also in mechanical engineering, especially in the machine-tool sector, and in automation. Synergistic effects resulting from the distribution of functions to multiple users, in particular control units, can be achieved in this context. The term used is “distributed systems.” Such distributed systems or networks are thus made up of the users and the bus system or multiple bus systems connecting those users. Communication between different stations or users is thus taking place more and more via a communication system, bus system, or network of this kind, over which the data to be transferred are transmitted in messages. This communication traffic on the bus system, access and receiving mechanisms, and error handling are regulated by a corresponding protocol, the name of the respective protocol often being used (as it also is here) as a synonym for the network or bus system itself.
In the automotive sector, for example, the controller area network (CAN) bus has become established as a protocol. This is an event-controlled protocol, i.e. protocol activities such as the sending of a message are initiated by events that originate outside the communication system. Unique access to the communication system or bus system is resolved by priority-based bit arbitration. A prerequisite for this is that a priority be assigned to the data being transferred, and thus to each message. The CAN protocol is very flexible, and it is thus easy to insert further users and messages as long as free priorities (message identifiers) still exist. The totality of all the messages to be sent in the network, with priorities and with their transmitting and receiving users and the corresponding communication modules, are stored in a list called the communication matrix.
An alternative approach to event-controlled, spontaneous communication is the exclusively time-controlled approach. All communication activities on the bus are strictly periodic. Protocol activities such as the sending of a message are triggered only by the passage of a time that applies to the bus system. Access to this medium is based on the apportioning of time regions in which a transmitter has an exclusive transmission right. As a rule, the message sequence must already be defined before initial startup. A schedule is therefore drawn up that meets the messages' requirements in terms of repetition rate, redundancy, deadlines, etc. This is called a “bus schedule.” One such bus system is, for example, TTP/C.
The advantages of both aforesaid bus types are combined in the time-controlled CAN approach, called TTCAN (time-triggered controller area network). This meets the requirements outlined above for time-controlled communication, and the requirements for a certain degree of flexibility. TTCAN achieves this by constructing the communication round in “exclusive” time windows for periodic messages of specific communication users, and in “arbitrating” time windows for spontaneous messages of multiple communication users. TTCAN is based substantially on a time-controlled, periodic communication that is timed, with the aid of a time-reference message, by a user or communication module (called the “time master”) that defines the principal time.
A further possibility for combining different transfer types is offered by the FlexRay protocol, which describes a fast, deterministic, and fault-tolerant bus system for use in particular in a motor vehicle. This protocol operates with the time division multiple access (TDMA) method, in which the users and the messages to be transferred are allocated fixed time slots in which they have exclusive access to the communication connection (the bus). The time slots repeat in a defined cycle, so that the point in time at which a message is transferred via the bus can be predicted exactly, and bus access occurs deterministically. For optimum utilization of the bandwidth for message transfer on the bus system, the cycle is subdivided into a static and a dynamic part. The fixed time slots are located in the static part at the beginning of a bus cycle. In the dynamic part, the time slots are assigned dynamically, and exclusive bus access therein is enabled for only a short time in each case. If no access occurs, access is authorized for the next user. This time span is referred to as a “mini-slot,” in which the system waits for access by the first user.
As just presented, a plurality of different transfer technologies, and therefore types of bus systems or networks, exist. It is often the case that multiple bus systems of the same or different types must be connected to one another. This purpose is served by a bus interface unit, called a “gateway.” A gateway is therefore an interface between different buses, which can be of the same or different types: the gateway forwards messages from one bus to one or more other buses. Known gateways are made up of multiple independent communication modules; the exchange of messages occurs via the processor interface (CPU interface) of the respective user or the corresponding interface module of the respective communication module. This CPU interface is heavily loaded by this data exchange in addition to the messages to be transferred to the user itself; in combination with the transfer structure resulting therefrom, this results in a relatively low data transfer speed. Integrated communication controllers or communication modules, which share a common message memory (also called message RAM) in order thereby to compensate for structural disadvantages, also exist.
FIG. 1 shows a gateway according to the existing art. The gateway contains multiple communication modules or communication controllers (CC), each of which is provided for connection of one serial bus. Data are transferred in packet fashion via the serial buses. The gateway contains an internal system bus for internal data transfer, the internal system bus encompassing a data bus DB, a control bus SB, and an address bus AB. Also connected to the system bus, in addition to the various communication modules CC, are a data processing unit CPU, data memory RAM, and further optional components. The CPU configures, monitors, and controls the individual communication modules CC. On internal data bus DB, data are transferred in word-based fashion between the various units. The number of data bits transferred in one data word corresponds to the bus width of data bus DB.
In the conventional gateway as depicted in FIG. 1, the CPU reads received messages, processes them, and generates new messages. The CPU also handles the delivery of messages. In simple gateway operations, received data are read out from a communication module CC and written into another, or several further, communication modules CC for delivery. If a DMA controller is not used, the host CPU transfers the data in word-based fashion from the communication modules CC into the data memory RAM or into a CPU-internal memory, in order to process the data and then copy them into the corresponding communication modules CC. The data memory RAM contains not only the transferred data but also a region for storing the program to be executed by the CPU.
Communication modules CC represent the connection from the gateway to the individual serial bus systems. These communication modules CC exchange data packets, which contain headers or administrative data and useful or payload data, with the serial data buses. In addition, communication modules CC have an interface to the system bus, i.e. to the control, data, and address buses. The host CPU can access, via a passive interface, a message memory contained respectively in communication module CC. The internal system bus, which encompasses data bus DB, control bus SB, and address bus AB, is connected to all the communication modules CC of the gateway. Data bus DB is made up of data lines from [sic] which data are transferred from one unit connected to the bus to another unit. The CPU controls data transfer by way of control bus SB. Address bus AB serves for selection of the data that are read out from a communication module CC or written into a communication module. The CPU receives or sends data by way of an internal CPU data register.
FIGS. 2 and 3 illustrate the execution of a data transfer in a conventional gateway according to the existing art. In the example depicted in FIGS. 2 and 3, data are being transferred from a serial field bus FB1 to a serial field bus FB2. What first happens, as depicted in FIG. 2, is a read access by the CPU to communication module CC1, which is connected to serial bus FB1. The CPU selects the data to be read by applying an address via address bus AB, and delivering the corresponding control signals to control bus SB. Communication module CC1 receives data (packaged in data packets DP) via serial field bus FB1, delivers the selected data, in one or more data words DW, onto internal data bus DB, and signals this to the status lines of control bus SB that correspond to the CPU. The CPU picks up the data pending on data bus DB, and stores them in an internal register of the CPU. The control signals on control bus DB are then reset.
In a second phase, the data transferred into the CPU register are then transferred to second communication module CC2. In the second bus transfer, the data read out from communication modules 1 are transferred out of the CPU's internal register to second communication module CC2. For this, the CPU applies the data to be transferred to data bus DB, and selects the corresponding destination address of the second communication module. The CPU then starts the data transfer by setting corresponding control lines of control bus SB. Second communication module CC2 picks up the data applied to the data bus, and signals this to the CPU once again by way of status lines of control bus SB. The CPU then resets the control lines, data lines, and address lines. Second communication module CC2 also resets the control signals on the status lines.
As may be gathered from FIGS. 2 and 3, in a conventional gateway a data transfer from a first field bus FB1 to a second field bus FB2 takes place in two phases, namely in a read operation in which data are read out by the CPU from first communication module 1, and in a write operation in which the read-out data are then written into second communication module CC2.
A disadvantage with the conventional procedure for transferring data with the conventional gateway according to the existing art depicted in FIG. 1 is that a data transfer between two serial field buses FB1, FB2 takes a relatively long time, and that the latency time required for the data transfer is relatively long. A further disadvantage of the conventional gateway is that the data transfer occurs via the CPU, i.e. the CPU experiences a load in the context of the data transfer, and cannot carry out any other data processing operations during that time.